The present invention relates to a FEMFET device (FEMFET=ferroelectric memory field-effect transistor) as described in the preamble of claim 1, which is known from EP 0 566 585 B1.
EP 0 566 585 B1 discloses, in general terms, a memory cell arrangement which, as memory cells, has field-effect transistors with a ferroelectric layer (FEMFETs) in the gate dielectric. In that document, it is recommended in particular for the gate dielectric to be designed as a multilayer dielectric, in which a first SiO2 layer is provided on the substrate, above which there is the ferroelectric layer, followed by a second SiO2 layer, to which the gate electrode, for example made from polycrystalline silicon, is applied.
Recently, in the microelectronics sector ferroelectric materials, generally perovskites, have been used to fabricate nonvolatile memory elements. The spontaneous and residual electrical polarization of these materials allows non-volatile storage of charge and therefore information. The ferroelectric materials are usually used either as dielectric layer in a capacitor or in the gate stack of a field-effect transistor.
A field-effect transistor with ferroelectric gate material forms the starting point for the construction of, for example, nonvolatile one-transistor memory cells with extremely short write,erase (unlike EEPROMs) and read times. The residual polarization of the ferroelectric material above the channel of a field-effect transistor and the resultant electric field allow different states, such as inversion or accumulation, to be xe2x80x9cstoredxe2x80x9d in the semiconductor substrate (channel) below. The operating state and the conductivity of the transistor can therefore undergo nonvolatile change through the ferroelectric. The fact that a component of this type can be used to store information and distinguish between logic states is attributable to this property. Information is stored by applying a sufficiently high voltage to the ferroelectric material. As a result, the polarization of the material can be changed (reversed) suitably.
The general problem on which the present invention is based is that of being able to eliminate the need to deposit ferroelectric material immediately above the channel, i.e. directly on the semiconductor substrate, in order to obtain functioning transistors or transistors with good electrical properties.
Poor interfacial properties destroy the function of the component.
Therefore, it has been proposed for one or more additional dielectric layers (what are known as dielectric buffer layers) to be provided between the substrate and the ferroelectric material. On the one hand, they are to ensure a sufficiently good interface with the silicon and therefore good transistor properties, yet on the other hand they are to have the minimum possible effect on the performance of the component.
Ferroelectric materials generally have a very high dielectric susceptibility (high relative dielectric constant xcex5r of a few hundred to 1000).
In the ferroelectric field-effect transistor, the semiconductor substrate, the dielectric buffer layer and the ferroelectric form a series circuit of different capacitances. To allow the polarization of the ferroelectric material to be changed using low voltages, it is therefore necessary for the dielectric buffer layer to have the highest possible xcex5r and a low layer thickness d, since otherwise most of a voltage which is applied to this combination of layers will drop off across the intermediate layer rather than across the ferroelectric. Otherwise, this leads to high programming voltages and the risk of electrical breakdowns in the layers. In particular, it should be ensured that the formation of natural or process-related SiO2 at the semiconductor substrate/intermediate layer interface is avoided, since SiO2 has an adverse effect on the properties of the transistor, i.e. leads to higher programming voltages, on account of its low xcex5r (high voltage drop). To bypass these problems, it has been proposed to use stable oxides with a high dielectric susceptibility, such as for example CeO2, Y2O3 or ZrO2, as dielectric buffer layer.
The fact that diffusion processes between individual constituents of the ferroelectric material and the semiconductor substrate likewise have a very adverse effect on the transistor properties has proven to be a drawback of the known approaches described above. Although this problem could be counteracted by increasing the layer thickness d of the dielectric buffer layer, this, as has been mentioned, would increase the risk of electrical breakdowns.
Therefore, it is an object of the present invention to improve the FEMFET device defined in the introduction in such a manner that the disruptive diffusion processes are eliminated without having an adverse effect on the electrical properties.
According to the invention, this object is achieved by the FEMFET device described in claim 1 and by the corresponding fabrication process described in claim 6.
Compared to the known solution approaches, the FEMFET device according to the invention has the advantage that there is no longer any disruptive diffusion and, at the same time, the gate stack does not become excessively thick.
The idea on which the present invention is based is for the gate stack to have at least one thin diffusion barrier layer which is arranged between the bottom ferroelectric layer and the semiconductor substrate. Depending on the ferroelectric used, the thin diffusion barrier layer is configured in such a manner that it substantially prevents constituents from diffusing out of the ferroelectric layer or layers into the semi-conductor substrate.
The subclaims provide advantageous refinements and improvements to the FEMFET device described in claim 1.
According to a preferred refinement, the diffusion barrier layer has a silicon nitride layer.
According to a further preferred refinement, the silicon nitride layer is provided directly on the semi-conductor substrate. The usual ferroelectric transistors are exclusively based on the use of ceramic oxides as dielectric intermediate layer. Silicon nitride in combination with prior cleaning of the substrate (removal of the natural oxide), as a new material at this location, offers many advantageous, in particular a good quality of the interface, a sufficiently high relative dielectric constant and, finally, its excellent action as a diffusion barrier even with very small layer thicknesses.
According to a further preferred refinement, at least one dielectric buffer layer is provided in the gate stack between the ferroelectric layer and the semi-conductor substrate. In this way, it is possible to increase the capacitance of the gate stack combined with simultaneous resistance to diffusion.
According to a further preferred refinement, the dielectric buffer layer is provided directly on the semiconductor substrate. This is expedient if the dielectric buffer layer and the semiconductor substrate have good interfacial properties.